Attachment 121012 Details for Bug 93599 – gen7_stall_before_ro_invalidation-2.patch

[patch] gen7_stall_before_ro_invalidation-2.patch

gen7_stall_before_ro_invalidation-2.patch (text/plain), 1.54 KB, created by Francisco Jerez on 2016-01-14 03:33:48 UTC

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Creator: Francisco Jerez

Created: 2016-01-14 03:33:48 UTC

Size: 1.54 KB

patch

obsolete

>diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
>index b63e61c..3f9ef59 100644
>--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
>+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
>@@ -328,6 +328,11 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
>    const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
>    const bool has_slm = cfg->n[L3P_SLM];
> 
>+   brw_emit_pipe_control_flush(brw,
>+                               PIPE_CONTROL_DATA_CACHE_INVALIDATE |
>+                               PIPE_CONTROL_NO_WRITE |
>+                               PIPE_CONTROL_CS_STALL);
>+
>    /* According to the hardware docs, the L3 partitioning can only be changed
>     * while the pipeline is completely drained and the caches are flushed,
>     * which involves a first PIPE_CONTROL flush which stalls the pipeline and
>@@ -337,9 +342,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
>                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
>                                PIPE_CONTROL_CONST_CACHE_INVALIDATE |
>                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
>-                               PIPE_CONTROL_DATA_CACHE_INVALIDATE |
>-                               PIPE_CONTROL_NO_WRITE |
>-                               PIPE_CONTROL_CS_STALL);
>+                               PIPE_CONTROL_NO_WRITE);
> 
>    /* ...followed by a second stalling flush which guarantees that
>     * invalidation is complete when the L3 configuration registers are

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Attachments on bug 93599: 120998 | 121012 | 121065

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