Attachment 16902 Details for Bug 16184 – Fixes from upstream ported back to 2.6.25

[patch] Fixes from upstream ported back to 2.6.25

i915-855GM-fixes.patch (text/plain), 2.28 KB, created by Jesse Barnes on 2008-06-03 18:25:59 UTC

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Creator: Jesse Barnes

Created: 2008-06-03 18:25:59 UTC

Size: 2.28 KB

patch

obsolete

>--- drivers/char/drm/i915_drv.c	2008-04-16 19:49:44.000000000 -0700
>+++ /home/jbarnes/working/linux-2.6/drivers/char/drm/i915_drv.c	2008-06-03 15:39:34.000000000 -0700
>@@ -147,7 +147,7 @@
> 	i915_write_indexed(cr_index, cr_data, 0x11,
> 			   i915_read_indexed(cr_index, cr_data, 0x11) &
> 			   (~0x80));
>-	for (i = 0; i < 0x24; i++)
>+	for (i = 0; i <= 0x24; i++)
> 		dev_priv->saveCR[i] =
> 			i915_read_indexed(cr_index, cr_data, i);
> 	/* Make sure we don't turn off CR group 0 writes */
>@@ -156,7 +156,7 @@
> 	/* Attribute controller registers */
> 	inb(st01);
> 	dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
>-	for (i = 0; i < 20; i++)
>+	for (i = 0; i <= 0x14; i++)
> 		dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
> 	inb(st01);
> 	outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
>@@ -206,7 +206,7 @@
> 	/* CRT controller regs */
> 	/* Enable CR group 0 writes */
> 	i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
>-	for (i = 0; i < 0x24; i++)
>+	for (i = 0; i <= 0x24; i++)
> 		i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
> 
> 	/* Graphics controller regs */
>@@ -223,7 +223,7 @@
> 
> 	/* Attribute controller registers */
> 	inb(st01);
>-	for (i = 0; i < 20; i++)
>+	for (i = 0; i <= 0x14; i++)
> 		i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
> 	inb(st01); /* switch back to index mode */
> 	outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
>@@ -256,6 +256,9 @@
> 	pci_save_state(dev->pdev);
> 	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
> 
>+	/* Display arbitration control */
>+	dev_priv->saveDSPARB = I915_READ(DSPARB);
>+
> 	/* Pipe & plane A info */
> 	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
> 	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
>@@ -349,6 +352,7 @@
> 	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
> 
> 	/* Clock gating state */
>+	dev_priv->saveD_STATE = I915_READ(D_STATE);
> 	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
> 
> 	/* Cache mode state */
>@@ -388,6 +392,8 @@
> 
> 	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
> 
>+	I915_WRITE(DSPARB, dev_priv->saveDSPARB);
>+
> 	/* Pipe & plane A info */
> 	/* Prime the clock */
> 	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
>@@ -507,6 +513,7 @@
> 	udelay(150);
> 
> 	/* Clock gating state */
>+	I915_WRITE (D_STATE, dev_priv->saveD_STATE);
> 	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
> 
> 	/* Cache mode state */

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Attachments on bug 16184: 16852 | 16853 | 16902 | 16985 | 16986 | 16987 | 16988 | 16989 | 16990 | 16991 | 17062

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