Running Steam on gentoo 64-bit STEAM_RUNTIME is disabled by the user Installing breakpad exception handler for appid(steam)/version(1382035714_client) [2013-10-19 18:05:04] Startup - updater built Oct 17 2013 10:40:21 [2013-10-19 18:05:04] Opted in to client beta 'publicbeta' via beta file FRAG 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [2 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 V_MBCNT_LO_U32_B32_e64 VGPR4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 VGPR4, -1, VGPR4 ; 480808C1 V_LSHR_B32_e64 VGPR5, SGPR11, 16, 0, 0, 0, 0 ; D22A0005 0201200B V_AND_B32_e32 VGPR5, 127, VGPR5 ; 360A0AFF 0000007F V_CMP_LT_I32_e64 SGPR0_SGPR1, VGPR4, VGPR5, 0, 0, 0, 0 ; D1020000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 SGPR0_SGPR1, SGPR0_SGPR1 ; BE802400 S_XOR_B64 SGPR0_SGPR1, EXEC, SGPR0_SGPR1 ; 8980007E V_ADD_I32_e64 VGPR4, SGPR12, VGPR4, 0, 0, 0, 0 ; D24A6A04 0202080C V_LSHLREV_B32_e32 VGPR4, 2, VGPR4 ; 34080882 V_LSHL_B32_e64 VGPR5, SGPR13, 2, 0, 0, 0, 0 ; D2320005 0201040D V_ADD_I32_e32 VGPR4, VGPR4, VGPR5 ; 4A080B04 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR8_SGPR9, 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X VGPR0, 0, -1, 0, -1, 0, 4, 4, VGPR4, SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 EXEC, EXEC, SGPR0_SGPR1 ; 88FE007E EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [2 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 V_MBCNT_LO_U32_B32_e64 VGPR4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 VGPR4, -1, VGPR4 ; 480808C1 V_LSHR_B32_e64 VGPR5, SGPR11, 16, 0, 0, 0, 0 ; D22A0005 0201200B V_AND_B32_e32 VGPR5, 127, VGPR5 ; 360A0AFF 0000007F V_CMP_LT_I32_e64 SGPR0_SGPR1, VGPR4, VGPR5, 0, 0, 0, 0 ; D1020000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 SGPR0_SGPR1, SGPR0_SGPR1 ; BE802400 S_XOR_B64 SGPR0_SGPR1, EXEC, SGPR0_SGPR1 ; 8980007E V_ADD_I32_e64 VGPR4, SGPR12, VGPR4, 0, 0, 0, 0 ; D24A6A04 0202080C V_LSHLREV_B32_e32 VGPR4, 2, VGPR4 ; 34080882 V_LSHL_B32_e64 VGPR5, SGPR13, 2, 0, 0, 0, 0 ; D2320005 0201040D V_ADD_I32_e32 VGPR4, VGPR4, VGPR5 ; 4A080B04 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR8_SGPR9, 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X VGPR0, 0, -1, 0, -1, 0, 4, 4, VGPR4, SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 EXEC, EXEC, SGPR0_SGPR1 ; 88FE007E EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) unlinked 0 orphaned pipes removing stale semaphore last operated on by process 3101 with name 0eBlobRegistryMutex_B40379FDA495CF55EB066C28A5A5B821 removing stale semaphore last operated on by process 3101 with name 0eBlobRegistrySignal_B40379FDA495CF55EB066C28A5A5B821 removing stale semaphore last operated on by process 3101 with name 0emSteamEngineInstance removing stale semaphore last operated on by process 3101 with name 0eSteamEngineLock Installing breakpad exception handler for appid(steam)/version(1382035714_client) [1019/180505:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation Looks like steam didn't shutdown cleanly, scheduling immediate update check [2013-10-19 18:05:04] Checking for update on startup [2013-10-19 18:05:04] Suche nach verfügbaren Updates... [2013-10-19 18:05:05] Download skipped: /client/steam_client_publicbeta_ubuntu12 version 1382035714, installed version 1382035714 [2013-10-19 18:05:05] Nothing to do [2013-10-19 18:05:05] Installation wird überprüft... [2013-10-19 18:05:05] Performing checksum verification of executable files [2013-10-19 18:05:05] Verification complete FRAG 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [2 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 V_MBCNT_LO_U32_B32_e64 VGPR4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 VGPR4, -1, VGPR4 ; 480808C1 V_LSHR_B32_e64 VGPR5, SGPR11, 16, 0, 0, 0, 0 ; D22A0005 0201200B V_AND_B32_e32 VGPR5, 127, VGPR5 ; 360A0AFF 0000007F V_CMP_LT_I32_e64 SGPR0_SGPR1, VGPR4, VGPR5, 0, 0, 0, 0 ; D1020000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 SGPR0_SGPR1, SGPR0_SGPR1 ; BE802400 S_XOR_B64 SGPR0_SGPR1, EXEC, SGPR0_SGPR1 ; 8980007E V_ADD_I32_e64 VGPR4, SGPR12, VGPR4, 0, 0, 0, 0 ; D24A6A04 0202080C V_LSHLREV_B32_e32 VGPR4, 2, VGPR4 ; 34080882 V_LSHL_B32_e64 VGPR5, SGPR13, 2, 0, 0, 0, 0 ; D2320005 0201040D V_ADD_I32_e32 VGPR4, VGPR4, VGPR5 ; 4A080B04 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR8_SGPR9, 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X VGPR0, 0, -1, 0, -1, 0, 4, 4, VGPR4, SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 EXEC, EXEC, SGPR0_SGPR1 ; 88FE007E EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [2 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 V_MBCNT_LO_U32_B32_e64 VGPR4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 VGPR4, -1, VGPR4 ; 480808C1 V_LSHR_B32_e64 VGPR5, SGPR11, 16, 0, 0, 0, 0 ; D22A0005 0201200B V_AND_B32_e32 VGPR5, 127, VGPR5 ; 360A0AFF 0000007F V_CMP_LT_I32_e64 SGPR0_SGPR1, VGPR4, VGPR5, 0, 0, 0, 0 ; D1020000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 SGPR0_SGPR1, SGPR0_SGPR1 ; BE802400 S_XOR_B64 SGPR0_SGPR1, EXEC, SGPR0_SGPR1 ; 8980007E V_ADD_I32_e64 VGPR4, SGPR12, VGPR4, 0, 0, 0, 0 ; D24A6A04 0202080C V_LSHLREV_B32_e32 VGPR4, 2, VGPR4 ; 34080882 V_LSHL_B32_e64 VGPR5, SGPR13, 2, 0, 0, 0, 0 ; D2320005 0201040D V_ADD_I32_e32 VGPR4, VGPR4, VGPR5 ; 4A080B04 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR8_SGPR9, 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X VGPR0, 0, -1, 0, -1, 0, 4, 4, VGPR4, SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 EXEC, EXEC, SGPR0_SGPR1 ; 88FE007E EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %22 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %23 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6) %24 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_P1_F32 VGPR2, VGPR0, 3, 0, [M0] ; C8080300 V_INTERP_P2_F32 VGPR2, [VGPR2], VGPR1, 3, 0, [M0] ; C8090301 V_INTERP_P1_F32 VGPR3, VGPR0, 2, 0, [M0] ; C80C0200 V_INTERP_P2_F32 VGPR3, [VGPR3], VGPR1, 2, 0, [M0] ; C80D0201 V_INTERP_P1_F32 VGPR4, VGPR0, 1, 0, [M0] ; C8100100 V_INTERP_P2_F32 VGPR4, [VGPR4], VGPR1, 1, 0, [M0] ; C8110101 V_INTERP_P1_F32 VGPR5, VGPR0, 0, 0, [M0] ; C8140000 V_INTERP_P2_F32 VGPR5, [VGPR5], VGPR1, 0, 0, [M0] ; C8150001 EXP 15, 0, 0, 1, 1, VGPR5, VGPR4, VGPR3, VGPR2 ; F800180F 02030405 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = fmul float %31, %12 %43 = fmul float %31, %13 %44 = fmul float %31, %14 %45 = fmul float %31, %15 %46 = fmul float %32, %16 %47 = fadd float %46, %42 %48 = fmul float %32, %17 %49 = fadd float %48, %43 %50 = fmul float %32, %18 %51 = fadd float %50, %44 %52 = fmul float %32, %19 %53 = fadd float %52, %45 %54 = fmul float %33, %20 %55 = fadd float %54, %47 %56 = fmul float %33, %21 %57 = fadd float %56, %49 %58 = fmul float %33, %22 %59 = fadd float %58, %51 %60 = fmul float %33, %23 %61 = fadd float %60, %53 %62 = fmul float %34, %24 %63 = fadd float %62, %55 %64 = fmul float %34, %25 %65 = fadd float %64, %57 %66 = fmul float %34, %26 %67 = fadd float %66, %59 %68 = fmul float %34, %27 %69 = fadd float %68, %61 %70 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000) %71 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000) %72 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000) %73 = call float @llvm.AMDIL.clamp.(float %41, float 0,000000e+00, float 0x3FF0000000000000) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %70, float %71, float %72, float %73) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR8_SGPR9_SGPR10_SGPR11, SGPR6_SGPR7, 4 ; C0840704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR8_SGPR9_SGPR10_SGPR11[VGPR0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 VGPR5, VGPR4, 0, 0, 1, 0, 0 ; D2060805 02010104 V_ADD_F32_e64 VGPR6, VGPR3, 0, 0, 1, 0, 0 ; D2060806 02010103 V_ADD_F32_e64 VGPR7, VGPR2, 0, 0, 1, 0, 0 ; D2060807 02010102 V_ADD_F32_e64 VGPR1, VGPR1, 0, 0, 1, 0, 0 ; D2060801 02010101 EXP 15, 32, 0, 0, 0, VGPR1, VGPR7, VGPR6, VGPR5 ; F800020F 05060701 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR6_SGPR7, 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR4_SGPR5_SGPR6_SGPR7[VGPR0] + 0 ; E00C2000 80010000 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR0_SGPR1, 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR4, SGPR4 ; 7E080204 V_MUL_F32_e64 VGPR4, VGPR0, VGPR4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR1, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR2, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR3, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MUL_F32_e64 VGPR5, VGPR0, VGPR5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR1, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR2, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR3, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MUL_F32_e64 VGPR6, VGPR0, VGPR6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR1, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR2, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR3, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MUL_F32_e64 VGPR7, VGPR0, VGPR7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR4 ; 7E100204 V_MAD_F32 VGPR7, VGPR1, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR4 ; 7E100204 V_MAD_F32 VGPR7, VGPR2, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD SGPR0, SGPR0_SGPR1_SGPR2_SGPR3, 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR0 ; 7E100200 V_MAD_F32 VGPR0, VGPR3, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, VGPR0, VGPR6, VGPR5, VGPR4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) %25 = call i32 @llvm.SI.packf16(float %21, float %22) %26 = bitcast i32 %25 to float %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 VGPR0, VGPR1, VGPR0 ; 5E000101 V_INTERP_MOV_F32 VGPR1, P0, 1, 0, [M0] ; C8060102 V_INTERP_MOV_F32 VGPR2, P0, 0, 0, [M0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 VGPR1, VGPR2, VGPR1 ; 5E020302 EXP 15, 0, 1, 1, 1, VGPR1, VGPR0, VGPR1, VGPR0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], CONST[4] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [2 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64) %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68) %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72) %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76) %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0 %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) %34 = fdiv float %31, %33 %35 = fdiv float %32, %33 %36 = bitcast float %34 to i32 %37 = bitcast float %35 to i32 %38 = insertelement <2 x i32> undef, i32 %36, i32 0 %39 = insertelement <2 x i32> %38, i32 %37, i32 1 %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %28, <16 x i8> %30, i32 2) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %41, %23 %46 = fmul float %42, %24 %47 = fmul float %43, %25 %48 = fmul float %44, %26 %49 = call i32 @llvm.SI.packf16(float %45, float %46) %50 = bitcast i32 %49 to float %51 = call i32 @llvm.SI.packf16(float %47, float %48) %52 = bitcast i32 %51 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_P1_F32 VGPR2, VGPR0, 1, 0, [M0] ; C8080100 V_INTERP_P2_F32 VGPR2, [VGPR2], VGPR1, 1, 0, [M0] ; C8090101 V_INTERP_P1_F32 VGPR3, VGPR0, 3, 0, [M0] ; C80C0300 V_INTERP_P2_F32 VGPR3, [VGPR3], VGPR1, 3, 0, [M0] ; C80D0301 V_RCP_F32_e32 VGPR3, VGPR3 ; 7E065503 V_MUL_F32_e32 VGPR5, VGPR2, VGPR3 ; 100A0702 V_INTERP_P1_F32 VGPR2, VGPR0, 0, 0, [M0] ; C8080000 V_INTERP_P2_F32 VGPR2, [VGPR2], VGPR1, 0, 0, [M0] ; C8090001 V_MUL_F32_e32 VGPR4, VGPR2, VGPR3 ; 10080702 S_LOAD_DWORDX4 SGPR8_SGPR9_SGPR10_SGPR11, SGPR2_SGPR3, 0 ; C0840300 S_LOAD_DWORDX8 SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, SGPR4_SGPR5, 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE VGPR0_VGPR1_VGPR2_VGPR3, 15, 0, 0, 0, 0, 0, 0, 0, VGPR4_VGPR5, SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, SGPR8_SGPR9_SGPR10_SGPR11 ; F0800F00 00430004 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR0_SGPR1, 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 19 ; C2020113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR4, SGPR4 ; 7E080204 V_MUL_F32_e64 VGPR4, VGPR3, VGPR4, 0, 0, 0, 0 ; D2100004 02020903 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 18 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MUL_F32_e64 VGPR5, VGPR2, VGPR5, 0, 0, 0, 0 ; D2100005 02020B02 V_CVT_PKRTZ_F16_F32_e32 VGPR4, VGPR5, VGPR4 ; 5E080905 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 17 ; C2020111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MUL_F32_e64 VGPR5, VGPR1, VGPR5, 0, 0, 0, 0 ; D2100005 02020B01 S_BUFFER_LOAD_DWORD SGPR0, SGPR0_SGPR1_SGPR2_SGPR3, 16 ; C2000110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR0 ; 7E0C0200 V_MUL_F32_e64 VGPR0, VGPR0, VGPR6, 0, 0, 0, 0 ; D2100000 02020D00 V_CVT_PKRTZ_F16_F32_e32 VGPR0, VGPR0, VGPR5 ; 5E000B00 EXP 15, 0, 1, 1, 1, VGPR0, VGPR4, VGPR0, VGPR4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = fmul float %31, %12 %43 = fmul float %31, %13 %44 = fmul float %31, %14 %45 = fmul float %31, %15 %46 = fmul float %32, %16 %47 = fadd float %46, %42 %48 = fmul float %32, %17 %49 = fadd float %48, %43 %50 = fmul float %32, %18 %51 = fadd float %50, %44 %52 = fmul float %32, %19 %53 = fadd float %52, %45 %54 = fmul float %33, %20 %55 = fadd float %54, %47 %56 = fmul float %33, %21 %57 = fadd float %56, %49 %58 = fmul float %33, %22 %59 = fadd float %58, %51 %60 = fmul float %33, %23 %61 = fadd float %60, %53 %62 = fmul float %34, %24 %63 = fadd float %62, %55 %64 = fmul float %34, %25 %65 = fadd float %64, %57 %66 = fmul float %34, %26 %67 = fadd float %66, %59 %68 = fmul float %34, %27 %69 = fadd float %68, %61 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR8_SGPR9_SGPR10_SGPR11, SGPR6_SGPR7, 4 ; C0840704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR8_SGPR9_SGPR10_SGPR11[VGPR0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR6_SGPR7, 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR4_SGPR5_SGPR6_SGPR7[VGPR0] + 0 ; E00C2000 80010000 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR0_SGPR1, 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR4, SGPR4 ; 7E080204 V_MUL_F32_e64 VGPR4, VGPR0, VGPR4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR1, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR2, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR3, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MUL_F32_e64 VGPR5, VGPR0, VGPR5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR1, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR2, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR3, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MUL_F32_e64 VGPR6, VGPR0, VGPR6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR1, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR2, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR3, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MUL_F32_e64 VGPR7, VGPR0, VGPR7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR4 ; 7E100204 V_MAD_F32 VGPR7, VGPR1, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR4 ; 7E100204 V_MAD_F32 VGPR7, VGPR2, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD SGPR0, SGPR0_SGPR1_SGPR2_SGPR3, 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR0 ; 7E100200 V_MAD_F32 VGPR0, VGPR3, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, VGPR0, VGPR6, VGPR5, VGPR4 ; F80008CF 04050600 S_ENDPGM ; BF810000 Generating new string page texture 2: 48x256, total string texture memory is 49,15 KB FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], IN[0] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %27 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6) %28 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) %29 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6) %30 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6) %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6) %32 = fdiv float %29, %31 %33 = fdiv float %30, %31 %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %22, <16 x i8> %24, i32 2) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = fmul float %39, %25 %44 = fmul float %40, %26 %45 = fmul float %41, %27 %46 = fmul float %42, %28 %47 = call i32 @llvm.SI.packf16(float %43, float %44) %48 = bitcast i32 %47 to float %49 = call i32 @llvm.SI.packf16(float %45, float %46) %50 = bitcast i32 %49 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %48, float %50, float %48, float %50) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_P1_F32 VGPR2, VGPR0, 1, 1, [M0] ; C8080500 V_INTERP_P2_F32 VGPR2, [VGPR2], VGPR1, 1, 1, [M0] ; C8090501 V_INTERP_P1_F32 VGPR3, VGPR0, 3, 1, [M0] ; C80C0700 V_INTERP_P2_F32 VGPR3, [VGPR3], VGPR1, 3, 1, [M0] ; C80D0701 V_RCP_F32_e32 VGPR3, VGPR3 ; 7E065503 V_MUL_F32_e32 VGPR5, VGPR2, VGPR3 ; 100A0702 V_INTERP_P1_F32 VGPR2, VGPR0, 0, 1, [M0] ; C8080400 V_INTERP_P2_F32 VGPR2, [VGPR2], VGPR1, 0, 1, [M0] ; C8090401 V_MUL_F32_e32 VGPR4, VGPR2, VGPR3 ; 10080702 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR2_SGPR3, 0 ; C0800300 S_LOAD_DWORDX8 SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15, SGPR4_SGPR5, 0 ; C0C40500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE VGPR2_VGPR3_VGPR4_VGPR5, 15, 0, 0, 0, 0, 0, 0, 0, VGPR4_VGPR5, SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15, SGPR0_SGPR1_SGPR2_SGPR3 ; F0800F00 00020204 V_INTERP_P1_F32 VGPR6, VGPR0, 3, 0, [M0] ; C8180300 V_INTERP_P2_F32 VGPR6, [VGPR6], VGPR1, 3, 0, [M0] ; C8190301 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 VGPR6, VGPR5, VGPR6 ; 100C0D05 V_INTERP_P1_F32 VGPR7, VGPR0, 2, 0, [M0] ; C81C0200 V_INTERP_P2_F32 VGPR7, [VGPR7], VGPR1, 2, 0, [M0] ; C81D0201 V_MUL_F32_e32 VGPR7, VGPR4, VGPR7 ; 100E0F04 V_CVT_PKRTZ_F16_F32_e32 VGPR6, VGPR7, VGPR6 ; 5E0C0D07 V_INTERP_P1_F32 VGPR7, VGPR0, 1, 0, [M0] ; C81C0100 V_INTERP_P2_F32 VGPR7, [VGPR7], VGPR1, 1, 0, [M0] ; C81D0101 V_MUL_F32_e32 VGPR7, VGPR3, VGPR7 ; 100E0F03 V_INTERP_P1_F32 VGPR8, VGPR0, 0, 0, [M0] ; C8200000 V_INTERP_P2_F32 VGPR8, [VGPR8], VGPR1, 0, 0, [M0] ; C8210001 V_MUL_F32_e32 VGPR0, VGPR2, VGPR8 ; 10001102 V_CVT_PKRTZ_F16_F32_e32 VGPR0, VGPR0, VGPR7 ; 5E000F00 EXP 15, 0, 1, 1, 1, VGPR0, VGPR6, VGPR0, VGPR6 ; F8001C0F 06000600 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: MOV OUT[2], IN[2] 6: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6) %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = extractelement <4 x float> %44, i32 2 %48 = extractelement <4 x float> %44, i32 3 %49 = fmul float %31, %12 %50 = fmul float %31, %13 %51 = fmul float %31, %14 %52 = fmul float %31, %15 %53 = fmul float %32, %16 %54 = fadd float %53, %49 %55 = fmul float %32, %17 %56 = fadd float %55, %50 %57 = fmul float %32, %18 %58 = fadd float %57, %51 %59 = fmul float %32, %19 %60 = fadd float %59, %52 %61 = fmul float %33, %20 %62 = fadd float %61, %54 %63 = fmul float %33, %21 %64 = fadd float %63, %56 %65 = fmul float %33, %22 %66 = fadd float %65, %58 %67 = fmul float %33, %23 %68 = fadd float %67, %60 %69 = fmul float %34, %24 %70 = fadd float %69, %62 %71 = fmul float %34, %25 %72 = fadd float %71, %64 %73 = fmul float %34, %26 %74 = fadd float %73, %66 %75 = fmul float %34, %27 %76 = fadd float %75, %68 %77 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000) %78 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000) %79 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000) %80 = call float @llvm.AMDIL.clamp.(float %41, float 0,000000e+00, float 0x3FF0000000000000) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %77, float %78, float %79, float %80) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %45, float %46, float %47, float %48) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %70, float %72, float %74, float %76) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR8_SGPR9_SGPR10_SGPR11, SGPR6_SGPR7, 4 ; C0840704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR8_SGPR9_SGPR10_SGPR11[VGPR0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 VGPR5, VGPR4, 0, 0, 1, 0, 0 ; D2060805 02010104 V_ADD_F32_e64 VGPR6, VGPR3, 0, 0, 1, 0, 0 ; D2060806 02010103 V_ADD_F32_e64 VGPR7, VGPR2, 0, 0, 1, 0, 0 ; D2060807 02010102 V_ADD_F32_e64 VGPR1, VGPR1, 0, 0, 1, 0, 0 ; D2060801 02010101 EXP 15, 32, 0, 0, 0, VGPR1, VGPR7, VGPR6, VGPR5 ; F800020F 05060701 S_LOAD_DWORDX4 SGPR8_SGPR9_SGPR10_SGPR11, SGPR6_SGPR7, 8 ; C0840708 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR8_SGPR9_SGPR10_SGPR11[VGPR0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800021F 04030201 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR6_SGPR7, 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR4_SGPR5_SGPR6_SGPR7[VGPR0] + 0 ; E00C2000 80010000 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR0_SGPR1, 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR4, SGPR4 ; 7E080204 V_MUL_F32_e64 VGPR4, VGPR0, VGPR4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR1, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR2, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MAD_F32 VGPR4, VGPR3, VGPR5, VGPR4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR5, SGPR4 ; 7E0A0204 V_MUL_F32_e64 VGPR5, VGPR0, VGPR5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR1, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR2, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MAD_F32 VGPR5, VGPR3, VGPR6, VGPR5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR6, SGPR4 ; 7E0C0204 V_MUL_F32_e64 VGPR6, VGPR0, VGPR6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR1, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR2, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MAD_F32 VGPR6, VGPR3, VGPR7, VGPR6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR7, SGPR4 ; 7E0E0204 V_MUL_F32_e64 VGPR7, VGPR0, VGPR7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR4 ; 7E100204 V_MAD_F32 VGPR7, VGPR1, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR4 ; 7E100204 V_MAD_F32 VGPR7, VGPR2, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD SGPR0, SGPR0_SGPR1_SGPR2_SGPR3, 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR8, SGPR0 ; 7E100200 V_MAD_F32 VGPR0, VGPR3, VGPR8, VGPR7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, VGPR0, VGPR6, VGPR5, VGPR4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 %36 = call i32 @llvm.SI.packf16(float %32, float %33) %37 = bitcast i32 %36 to float %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_P1_F32 VGPR3, VGPR0, 1, 0, [M0] ; C80C0100 V_INTERP_P2_F32 VGPR3, [VGPR3], VGPR1, 1, 0, [M0] ; C80D0101 V_INTERP_P1_F32 VGPR2, VGPR0, 0, 0, [M0] ; C8080000 V_INTERP_P2_F32 VGPR2, [VGPR2], VGPR1, 0, 0, [M0] ; C8090001 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR2_SGPR3, 0 ; C0800300 S_LOAD_DWORDX8 SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, SGPR4_SGPR5, 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE VGPR0_VGPR1_VGPR2_VGPR3, 15, 0, 0, 0, 0, 0, 0, 0, VGPR2_VGPR3, SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, SGPR0_SGPR1_SGPR2_SGPR3 ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 VGPR4, VGPR2, VGPR3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 VGPR0, VGPR0, VGPR1 ; 5E000300 EXP 15, 0, 1, 1, 1, VGPR0, VGPR4, VGPR0, VGPR4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 %36 = call i32 @llvm.SI.packf16(float %32, float %33) %37 = bitcast i32 %36 to float %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_P1_F32 VGPR3, VGPR0, 1, 0, [M0] ; C80C0100 V_INTERP_P2_F32 VGPR3, [VGPR3], VGPR1, 1, 0, [M0] ; C80D0101 V_INTERP_P1_F32 VGPR2, VGPR0, 0, 0, [M0] ; C8080000 V_INTERP_P2_F32 VGPR2, [VGPR2], VGPR1, 0, 0, [M0] ; C8090001 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR2_SGPR3, 0 ; C0800300 S_LOAD_DWORDX8 SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, SGPR4_SGPR5, 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE VGPR0_VGPR1_VGPR2_VGPR3, 15, 0, 0, 0, 0, 0, 0, 0, VGPR2_VGPR3, SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, SGPR0_SGPR1_SGPR2_SGPR3 ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 VGPR4, VGPR2, VGPR3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 VGPR0, VGPR0, VGPR1 ; 5E000300 EXP 15, 0, 1, 1, 1, VGPR0, VGPR4, VGPR0, VGPR4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 Generating new string page texture 3: 256x256, total string texture memory is 311,30 KB Installing breakpad exception handler for appid(steam)/version(1382035714_client) Installing breakpad exception handler for appid(steam)/version(1382035714_client) local (potentially out of sync) copy of roaming config loaded - 3371 bytes. (steam:3237): GLib-GObject-WARNING **: /tmp/portage/dev-libs/glib-2.36.4-r1/work/glib-2.36.4/gobject/gsignal.c:2475: signal `child-added' is invalid for instance `0xa952048' of type `GtkMenu' Adding license for package 0 Adding license for package 172 Adding license for package 219 Adding license for package 715 Adding license for package 1045 Adding license for package 1062 Adding license for package 1535 Adding license for package 1995 Adding license for package 2482 Adding license for package 6098 Adding license for package 6428 Adding license for package 7802 Adding license for package 8535 Adding license for package 8539 Adding license for package 11072 Adding license for package 11144 Adding license for package 11856 Adding license for package 12518 Adding license for package 13408 Adding license for package 13509 Adding license for package 13510 Adding license for package 14786 Adding license for package 14795 Adding license for package 14866 Adding license for package 14963 Adding license for package 14981 Adding license for package 15051 Adding license for package 15101 Adding license for package 15103 Adding license for package 15933 Adding license for package 15996 Adding license for package 16354 Adding license for package 16531 Adding license for package 16549 Adding license for package 16589 Adding license for package 17250 Adding license for package 17483 Adding license for package 17484 Adding license for package 17485 Adding license for package 17486 Adding license for package 17804 Adding license for package 17843 Adding license for package 17968 Adding license for package 18082 Adding license for package 18095 Adding license for package 18447 Adding license for package 18555 Adding license for package 18557 Adding license for package 18876 Adding license for package 18998 Adding license for package 18999 Adding license for package 25544 Adding license for package 26394 Adding license for package 26464 Adding license for package 26827 Adding license for package 27214 Adding license for package 27306 Adding license for package 27437 Adding license for package 27530 Adding license for package 30286 Adding license for package 33322 Adding license for package 33373 roaming config store loaded successfully - 3371 bytes. migrating temporary roaming config store Installing breakpad exception handler for appid(steam)/version(1382035714_client) ExecCommandLine: "/home/lukas/.local/share/Steam/ubuntu12_32/steam" System startup time: 4,73 seconds FRAG 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* inreg, [2 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [2 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 V_MBCNT_LO_U32_B32_e64 VGPR4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 VGPR4, -1, VGPR4 ; 480808C1 V_LSHR_B32_e64 VGPR5, SGPR11, 16, 0, 0, 0, 0 ; D22A0005 0201200B V_AND_B32_e32 VGPR5, 127, VGPR5 ; 360A0AFF 0000007F V_CMP_LT_I32_e64 SGPR0_SGPR1, VGPR4, VGPR5, 0, 0, 0, 0 ; D1020000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 SGPR0_SGPR1, SGPR0_SGPR1 ; BE802400 S_XOR_B64 SGPR0_SGPR1, EXEC, SGPR0_SGPR1 ; 8980007E V_ADD_I32_e64 VGPR4, SGPR12, VGPR4, 0, 0, 0, 0 ; D24A6A04 0202080C V_LSHLREV_B32_e32 VGPR4, 2, VGPR4 ; 34080882 V_LSHL_B32_e64 VGPR5, SGPR13, 2, 0, 0, 0, 0 ; D2320005 0201040D V_ADD_I32_e32 VGPR4, VGPR4, VGPR5 ; 4A080B04 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR8_SGPR9, 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X VGPR0, 0, -1, 0, -1, 0, 4, 4, VGPR4, SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 EXEC, EXEC, SGPR0_SGPR1 ; 88FE007E EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([2 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 Running Steam on gentoo 64-bit STEAM_RUNTIME is disabled by the user Generating new string page texture 72: 128x256, total string texture memory is 131,07 KB Generating new string page texture 73: 128x256, total string texture memory is 442,37 KB Generating new string page texture 74: 8x256, total string texture memory is 450,56 KB Generating new string page texture 75: 32x256, total string texture memory is 483,33 KB ExecCommandLine: "/home/lukas/.steam/root/ubuntu12_32/steam steam://open/driverhelperready" ExecSteamURL: "steam://open/driverhelperready" [1019/180513:ERROR:cef_context.cc(499)] No data resource available for id 4501 Installing breakpad exception handler for appid(steam)/version(1382035714_client) Generating new string page texture 93: 256x256, total string texture memory is 393,22 KB Generating new string page texture 99: 128x256, total string texture memory is 614,40 KB Generating new string page texture 100: 64x256, total string texture memory is 679,94 KB Generating new string page texture 102: 48x256, total string texture memory is 729,09 KB Generating new string page texture 103: 128x256, total string texture memory is 860,16 KB Generating new string page texture 104: 256x256, total string texture memory is 1,12 MB Generating new string page texture 105: 384x256, total string texture memory is 1,52 MB Generating new string page texture 129: 256x256, total string texture memory is 1,78 MB Generating new string page texture 133: 128x256, total string texture memory is 1,91 MB Game update: AppID 209080 "Guns of Icarus Online", ProcID 3346, IP 0.0.0.0:0 Set current directory to /home/lukas/.local/share/Steam/SteamApps/common/Guns of Icarus Online Found path: /home/lukas/.local/share/Steam/SteamApps/common/Guns of Icarus Online/GunsOfIcarusOnline Mono path[0] = '/home/lukas/.local/share/Steam/SteamApps/common/Guns of Icarus Online/GunsOfIcarusOnline_Data/Managed' Mono path[1] = '/home/lukas/.local/share/Steam/SteamApps/common/Guns of Icarus Online/GunsOfIcarusOnline_Data/Mono' Mono config path = '/home/lukas/.local/share/Steam/SteamApps/common/Guns of Icarus Online/GunsOfIcarusOnline_Data/Mono/etc'